Key Tasks and Responsibilities

As part of the Microelectronics Section, you will have the following responsibilities:

• Technical and administrative management of the ESA Systems and synthesizable VHDL IP Core pool of designs. This work will involve: optimization, update and overall maintenance and of the ESA VHDL IP Cores databases, provision of technical support to ESA IP Cores users (performing analysis and finding solutions to problems in VHDL code, documentation or design methodology) holding a strong collaboration with our Contracts department in arranging and solving licenses and patent issues. Advertising the ESA IP service (website, workshops, etc.), handling IP cores requests and their distribution;
• Support ASIC and/or FPGA technology developments for R&D and /or projects, supervising that good design practices and manufacturing and test methodologies are applied. In addition, independent verification (through code inspection, simulation and timing analysis) and validation (through HW tests) will have to be carried out for some ASIC and FPGAS developments;
• Support development contracts regarding the above areas, act as the activity technical responsible, maintain interfaces with the prime contractors, participate in progress meetings and reviews, as requested, and provide appropriate feedback on the achieved progress and discussions;
• Supporting projects, interface with ESA’s project teams, the prime and lower level contractors, participate in progress meetings and reviews, as requested by project work, and provide appropriate feedback on the achieved progress and discussions.

Skills & Experience

You will have the following qualifications and relevant experience:

• Master's degree in Electronics Engineering or Physics, specialized in digital signal processing and microelectronics, with five or more years of experience in at least three of the following domains:
  • Development of digital signal processing architecture, simulation, implementation and validation, including the coding into a hardware description language (HDL);
  • Development of functional and performance test cases and benches for the verification, profiling and validation of the digital signal processing architecture;
  • Design and test of digital FPGAs and ASICs (specifications, block design, top level integration, design for test, pre and post layout simulation and timing analysis, gates synthesis, support during layout, prototype test and in system validation), with proficiency in HDL (VHDL, Verilog and System-C);
  • VLSI IC Design CAD tools such as: Synopsys, CADENCE, Mentor, MATLAB and/or Simulink as well as hardware description languages (VHDL, Verilog, SystemVerilog, SystemC, …);
  • FPGA HW and SW of several vendors such as: Xilinx, Microchip (former Microsemi, former ACTEL) and/or NanoXplore;
  • Preparation of digital FPGA and ASIC design test-benches, for functional verification, validation and electrical characterization, using signal generators, oscilloscopes and signal analyzers;
  • System administration in UNIX and Windows for IC Design CAD tools.
• Fluency in English is mandatory; knowledge of another European language is an advantage

This job is located in Noordwijk.

If you think you have what it takes for this job, please send your CV (in English and in Word or PDF) to Viktoria Panicharova, by clicking on the button “Apply for this job” quoting job NL-HP-4992.

An exciting and dynamic international working environment awaits you!